1. Field of the Invention
The present invention relates to a clock distributor circuit, and more particularly to a clock distributor circuit that works with power consumption reduced for use in semiconductor logic circuitry including a clock synchronous circuit. The present invention also relates to a method for the same.
2. Description of the Background Art
Conventionally, logic circuits formed by system LSI (Large Scale Integration), such as a central processor unit (CPU) or digital signal processor (DSP), operative in response to a clock signal usually includes a clock synchronous circuit, which may be composed of flip-flop circuits. For those flip-flop circuits, a type of flip-flop circuit may be applicable which has its data input terminal D, clock input terminal C and data output terminal Q and controls clock synchronization in response to a clock signal inputted to the clock input terminal C. This clock signal is applied in common to all of the flip-flop circuits provided in the circuitry that need clock synchronous control, so that the clock synchronization is established for those circuits by the same clock signal.
As shown in FIG. 8, for example, a clock distributor circuit 400 to which such clock synchronous circuits are applied has flip-flop circuits 402 and 404 functioning as the clock synchronous circuits. The flip-flop circuits 402 and 404 are responsive to the clock signal CLK inputted via delay circuits 406 and 408, respectively, to control clock synchronization on data signals. In the illustrative clock distributor, the clock signal and the data signals are dealt with which have the waveforms thereof shown in FIG. 9.
In the clock distributor circuit 400, first, the data signal DATA1 is inputted to the input terminal D of the flip-flop circuit 402. The flip-flop circuit 402 is responsive to the positive-going edge A of the clock signal CLK, as shown in FIG. 9, to take in the data signal DATA1 and output the output signal DATA2 in synchronism with the positive-going edge A from its output terminal Q. The output data signal DATA2 is operationally processed by the combined logics 410, and the resultant output data signal DATA3 is then delivered to the input terminal D of the flip-flop circuit 404. In the flip-flop circuit 404, as shown in FIG. 9, the data signal DATA3 is taken in in response to the positive-going edge B of the clock signal CLK, and the output signal DATA4 is outputted from the output terminal Q in synchronism with the positive-going edge B. As described above, in the clock synchronous circuit, a data signal is outputted from the preceding flip-flop in response to the positive-going edge of the clock signal CLK, and is operationally processed prior to the next positive-going edge, the operational result then being taken in by the following flip-flop in response to the next positive-going edge.
The clock signal CLK is thus supplied to all of the clock signal input terminals C of the flip-flop circuits provided in the clock distributor circuit 400. When this circuit is applied to a system logic, however, it operates in such a complex and diversified manner that the extensive space is required for the circuit in proportion to a remarkable increase of its circuit scale. Further, as the flip-flop circuits are distributed throughout in the circuit, they have different distances from the clock signal source. Therefore, between the input timings of the clock signal CLK to those flip-flop circuits, some differences in delay are involved, which are referred to clock skew. To reduce the clock skew, as shown in FIG. 8, each clock synchronous circuit is interconnected to a corresponding delay circuit to adjust the input timing of the clock signal CLK. For example, in order to reduce the clock skew, a delay circuit is provided which consists of fewer delay elements for the flip-flop circuit located farther from the clock signal source, whereas another delay circuit is provided consisting of more delay elements for the flip-flop circuit nearer to the clock signal source.
Further, since the clock signal CLK is always being supplied during the LSI logic circuit working, power is always consumed on the clock lines from the clock signal source to each clock signal input terminal. In order to reduce the power consumption, the clock gating method is used as a technique to halt the clock signal CLK supplied to unused circuits. As shown in FIG. 10, a clock distributor circuit 500 structured on the basis of the clock gating method is composed of the gated clock circuits 510 and 512 which are respectively connected to the one couple of clock synchronous circuits 502 and 504 and the other couple of clock synchronous circuits 506 and 508.
To the gated clock circuits 510 and 512, the clock signal CLK and the clock enable signals 530 and 534 are inputted. Only when the clock enable signal becomes enabled, each gated clock circuit generates the gated clock signal to supply it to the clock signal input terminals of the associated clock synchronous circuits. It is therefore able to reduce power consumption which would otherwise be caused by toggling of the clock signal supplied to circuits which are provided with the clock synchronous circuits but not operative.
In the clock distributor circuit 500 based upon the clock gating method like this, the gated clock circuits 510 and 512 may be provided with delay circuits 524 and 526 to adjust the input timing of the clock signal CLK. Also, the clock synchronous circuits 502, 504, 506 and 508 may respectively be provided with delay circuits 516, 518, 520 and 522 to adjust the input timing of the gated clock signal.
For example, an ordinary gated clock control circuit disclosed in Japanese patent laid-open publication No. 2003-108259 controls the output clock timing in response to the ordinary gated clock control signal. In the gated clock control circuit disclose, when an input clock signal g is inputted to the inverted clock terminal CK of the flip-flop circuit 10-3, FIG. 8 thereof, and the ordinary gated control signal e is inputted to the input terminal D, the output signal is outputted from the output terminal Q of the flip-flop circuit 10-3. In response to this output signal, the output clock signal X is outputted from the logical product circuit.
Also, in the gated clock control circuit like this, after a certain stable period has elapsed, the control signal h supplied to the reset terminal R of the flip-flop circuit 7 is made to be its logical “1”, next the control signal f supplied to the logical product circuit 8 is made to be its logical “1” and then the ordinary gated clock control signal e is made to be its logical “1”. In turn, the output clock signal i is outputted from the logical product circuit 9. Further, when the ordinary gated clock control signal e is made to be its logical “0”, in response the output clock signal i is stopped, and then the control signals f and h are rendered to be its logical “0”.
Therefore, if there is noise included in the input clock signal g at its start and/or stop point in time, the ill effect that would otherwise be caused by the noise can be prevented. It is thus able to start and stop the oscillator optionally, thus providing an information processing apparatus with low-power consumption.
In semiconductor logic circuits, however, a significant proportion of the power is generally consumed by the clock lines against the whole circuitry. For example, approximately 30 percent of the whole power is consumed by the toggling of the clock signal. Also in general, the power consumption in the delay circuits provided ahead of the gated clock circuits is approximately ten times as much as that of the delay circuits provided behind of the gated clock circuits because the toggling rate after the gated clock circuit is remarkably smaller than that before the gated clock circuit. Therefore, in order to reduce the power consumption more effectively, it is necessary to reduce the power consumed in the delay circuits provided ahead of the gated clock circuits.